In particular, in an EEPROM memory, the memory cells are arranged according to word lines and according to bit columns transverse to the word lines. The memory cells of a bit column are coupled to a common bit line. The memory further comprises a line decoder to select a word line, a column decoder to select a bit line, and selection transistors controlled by the column decoder to couple the sense amplifier to a selected bit line.
Each memory cell comprises a floating-gate transistor coupled in series with a MOS-type access transistor. The floating-gate transistor comprises a floating gate and a control gate CG formed on the floating gate.
All the memory cells of a block, grouping together all or part of the memory cells of the memory, can be erased simultaneously by putting the control gate of all the floating-gate transistors of the block to a certain potential. The checking of this operation involves reading all the memory cells of the erased block.
Now, a memory cell is read by selecting the memory cell and by coupling it to a sense amplifier. As the memory only comprises a limited number of sense amplifiers, this checking operation requires a number of read cycles at least equal to the number of memory cells to be checked, divided by the number of sense amplifiers. Moreover, if all the erased memory cells are coupled to a same bit line, only one sense amplifier can be used. As a result, the number of read cycles required to check each of the erased memory cells is equal to the number of memory cells to be checked.
When the number of memory cells erased simultaneously is high, it is often not possible to check such an erasing operation.